1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a post package repair control circuit and a post package repair method.
2. Description of the Related Art
In a conventional post package repair method related to a semiconductor memory device, a mass-production package test is conducted in order to identify and collect failed package memory products. Next, the failed package memory products are retested using expensive test equipment having a storage device, e.g., a fail bit map memory, and failed bit information regarding the memory cells in the failed package memory products is stored in the storage device, i.e., the fail bit map memory. The failed bit information is read from the fail bit map memory and then failed memory cells corresponding to the failed bit information are repaired. An example of a technique of repairing failed memory cells has been disclosed in U.S. Pat. No. 6,788,596 B2.
The conventional post package repair method not only requires expensive test equipment having a storage device (a fail bit map memory) but also requires a lot of time conducting a mass-production package test, retesting using the expensive test equipment, and then performing repairs. Accordingly, gains obtained by performing post package repairs are less than losses caused by using expensive test equipment having a fail bit map memory.